1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
The degree of integration of semiconductor integrated circuits, particularly, integrated circuits using metal oxide semiconductor (MOS) transistors continues to increase. With the increase in the degree of integration, MOS transistors used in such integrated circuits have been miniaturized to the nanometer scale. Such miniaturization of MOS transistors makes it difficult to suppress leak current and causes an issue in that the area occupied by the circuits is not easily reduced because of a requirement to provide a necessary amount of current. To address such an issue, a surrounding gate transistor (hereinafter, referred to as an “SGT”) has been proposed which has a structure in which a source, a gate, and a drain are arranged vertically with respect to a substrate and an gate electrode surrounds a pillar-shaped semiconductor layer (see, for example, Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
In existing inverters using SGTs, a single transistor is formed for a single silicon pillar, and an nMOS transistor constituted by a single silicon pillar and a pMOS transistor constituted by a single silicon pillar are formed on a plane (see, for example, Japanese Unexamined Patent Application Publication No. 2008-300558). Since at least two silicon pillars are formed on a plane, an area for the at least two silicon pillars is needed.
In existing nonvolatile memory devices, a plurality of gates are formed for a single silicon pillar (see, for example, Japanese Unexamined Patent Application Publication No. 2014-57068). A gate insulating film is formed on the sidewall of the silicon pillar, and a source line and a bit line are connected to an upper end and a lower end of the silicon pillar.